SEMINAR: Dynamically configurable architectures for multi-GNSS receivers

ACSER Namuru Receivers - Evolution
ACSER Namuru Receivers - Evolution
29 March 2017 - 1:00pm to 2:00pm
Electrical Engineering Building, Room G3

Dynamically configurable architectures for multi-GNSS receivers

This presentation has focused on the development of dynamically configurable and programmable architectures for multi-GNSS receivers. The effect of RF front-end architecture and new characteristics of GNSS signals (modulation type, primary code generation, secondary code, required bandwidth and sampling frequency) on the complexity of the baseband receiver are analysed as a first step to developing the best architecture for a multi-GNSS receiver.

Several architectures are examined to derive the best model for multi-GNSS implementation, especially the underlying baseband and software realisations. Multicore and multiple processor architectures are shown to be promising candidates. General purpose processors or digital signal processors demand excessive resource and power consumption. Alternative architectures are presented along with a general cost function that is used to evaluate architecture efficiency based on six aspects: programmability, development cost, energy consumption, resource utilization, input/output latency and memory capacity requirement.   

Two custom channel architectures are proposed. A fully programmable channel core is more flexible, but processing constraints, high power, and resource consumption are the main drawbacks. A combination of a pipeline custom correlator and a custom core controller is a much more promising design. This programmable pipeline correlator combined with a proposed dynamically configurable moving average (MAV) decimator, which downsamples the baseband signal to any power of two division of the sampling frequency, can be multiplexed to process 16 GPS L1 C/A, 8 BEIDOU B1I, 4 GALILEO E1 or 1 GPS L5/GALILEO E5a/E5b channels. Not only are flexibility and programmability achieved, but resource utilisation is considerably reduced (45% to 96.5%) and power consumption is also reduced compared with other conventional digital architectures (52% to 67%). 

Furthermore, effects of sampling frequency, Doppler shift, integration and dump period, radio frequency (RF) front-end filter bandwidth, and received carrier to noise ratio ($C/N_0$) on the correlation output, as well as Delay Locked Loop (DLL) discrimination function and DLL tracking loop errors are re-estimated from a hardware perspective to accurately evaluate GNSS receiver performance. Consequently, novel solutions to mitigate the effect of the commensurate sampling frequency on DLL tracking loop error are proposed.


Vinh Tran is a PhD candidate in the School of Electrical Engineering and Telecommunications at the University of New South Wales (UNSW). He received B.Eng. (2007) in Computer Science and M.Sc. (2009) in Information Processing and Communication from the School of Information and Communication Technology, Hanoi University of Science and Technology. Currently. He is currently associated with Australian Centre for Space Engineering Research (ACSER) and Satellite Navigation and Positioning (SNAP) Laboratory. Click here to see Vinh's full profile.